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document : 1g5-0154 rev.1 page 1 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram description the device is cmos synchronous dynamic ram organized as 8,388,608 - word x 4 -bit x 4 - bank, 4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. these various organizations provide wide choice for different applications. it is designed with the state-of-the-art technology to meet stan- dard pc100 or high speed pc133 requirement. four internal independent banks greatly increase the perfor- mance efficiency. it is pa c kaged in jedec standard pinout and standard plastic 54-pin tsop package. features ? single 3.3v () power supply ? high speed clock cycle time : 7.5ns/10ns ? fully synchronous with all signals referenced to a positive clock edge ? programmable cas iatency (2,3) ? programmable burst length (1,2,4,8,& full page) ? programmable wrap sequence (sequential/interleave) ? automatic precharge and controlled precharge ? auto refresh and self refresh modes ? quad internal banks controlled by ba0 & ba1 (bank select) ? each bank can be operated simultaneously and independently ? i/o level : lvttl compatible ? random column access in every cycle ? x4, x8, x16 organization ? input/output controlled by dqm ( ldqm, udqm ) ? 4,096 refresh cycles/64ms ? burst termination by burst stop and precharge command ? burst read/single write option the information shown is subject to change without notice. 0.3v
document : 1g5-0154 rev.1 page 2 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram pin description vg36128801/vg36128161 pin name function pin name function a 0 - a 11 bao, ba1 address inputs bank select dqm, ldqm, udqm, upper dq mask enable, lower dq mask enable dq 0 ~ dq 15 data - in/data - out clk clock input ras row address strobe cke clock enable cas column address strobe cs chip select we write enable v ddq supply voltage for dq v ss ground v ssq ground for dq v dd power (+ 3.3v) v dd dq0 v ddq v ssq dq2 v ddq cas ras we a 10 ba0 a 1 a 2 a 3 v dd v ss v ssq v ddq dq11 v ss dq9 v ddq nc clk udqm cke nc v ss a 9 a 8 a 7 a 6 a 5 a 11 dq1 dq3 v ssq v dd ldqm cs ba1 a 0 a 4 v ssq dq13 dq15 vg36128161 (x 16) v dd dq0 v ddq v ssq dq2 v ddq nc cas ras we a 10 a 1 a 2 a 3 v dd nc dq1 nc dq3 v ssq nc v dd nc cs ba1 a 0 v ss v ssq v ddq dq5 v ss dq4 v ddq clk dqm cke nc v ss a 9 a 8 a 7 a 6 a 5 a 11 nc a 4 nc nc nc v ssq dq6 dq7 nc dq14 dq12 dq10 dq8 dq4 dq5 dq6 dq7 ba0 vg36128801 (x 8) p in configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 44 43 42 23 24 25 26 27 29 28 31 30 36 35 34 33 32 38 37 39 40 41 46 45 47 48 49 50 51 52 53 54 15 vg36128401 (x 4) v dd nc v ddq v ssq dq2 v ddq nc cas ras we a 10 a 1 a 2 a 3 v dd nc dq1 nc dq3 v ssq nc v dd nc cs ba1 a 0 ba0 v ss v ssq v ddq dq5 v ss dq4 v ddq clk dqm cke nc v ss a 9 a 8 a 7 a 6 a 5 a 11 nc a 4 nc nc nc v ssq dq6 dq7 nc
document : 1g5-0154 rev.1 page 3 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram block diagram clk cke clock generator cs ras mode register column address buffer & burst counter cas we c o m m a n d d e c o d e r c o n t r o l l o g i c address row address buffer & refresh counter bank b bank a sense amplifier column decoder & latch circuit r o w d e c o d e r data control circuit dq dqm l a t c h c i r c u i t i n p u t & o u t p u t b u f f e r (bank c) (bank d)
document : 1g5-0154 rev.1 page 4 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram absolute maximum d.c. ratings caution: exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 to + 4.6 v supply voltage relative to vss v dd , v ddq -0.5 to + 4.6 v short circuit output current i out 50 ma power dissipation p d 1.0 w operating temperature t opt 0 to + 70 j storage temperature t stg -55 to + 125 j maximum a.c. operating requirements for lvttl compatible parameter symbol min max unit notes input high voltage v ih 2.0 v dd + 0.3 v 1 input low voltage v il -0.3 0.8 v 2 r ecommended dc operating conditions for lvttl co mpatible parameter symbol min typ max unit supply voltage v dd, v ddq 3.0 3.3 3.6 v input high voltage, all inputs v ih 2.0 ?e v dd + 0.3 v input low voltage, all inputs v il -0.3 ?e 0.8 v capacitance (ta=25c, f = 1mhz) notes : 1. capacitance measured with effective capacitance measuring method. parameter symbol min max unit notes input capacitance (clk) c 11 2.5 4 pf 1 input capacitance (all input pins except data pins.) c 12 2.5 5 pf 1 data input/output capacitance c i/o 4.0 6.5 pf 1 note: 1. overshoot limit: v ih (max)=v ddq +2.0v with a pulse with 2. undershoot limit: v il (min)=v ssq -2.0v with a pulse with and -1.5v with a pulse 3ns < 3ns < 5ns <
document : 1g5-0154 rev.1 page 5 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test conditions -75 -8h unit notes min max min max operating current i cc1 burst length = 1 one bank active t rc t rc (min .) , io = 0ma x4 120 100 ma 1 x 8 125 105 x16 135 115 precharge standby current in power down mode i cc2p cke v il(max.) t ck = min. 2 2 ma i cc2ps cke v il(max.) t ck = 2 2 precharge standby current in nonpower down mode i cc2n cke v ih(min.) t ck = min. cs v ih(min.) input signals are changed one time during 2 clk cycles. 20 20 ma i cc2ns cke v ih(min.) t ck = clk v il(max.) input signals are stable. 7 7 active standby current in power down mode i cc3p cke v il(max.) t ck = min. 7 7 ma i cc3ps cke v il(max.) t ck = 5 5 active standby current in nonpower down mode i cc3n cke v ih(min.) t ck = min. cs v ih(min.) input signals are changed one time during 2clks 30 30 ma i cc3ns cke v ih(min.) t ck = clk v il(max.) input signals are stable. 20 20 operating current (burst mode) i cc4 t ck t ck(min.) io = 0ma all banks active x4 115 105 x 8 130 120 ma 2 x16 160 150 refresh current i cc5 t rc = 4 x t rc(min) 190 190 ma 3 self refresh current i cc6 cke 0.2v 1 1 ma input ieakage current (inputs) l li v in 0, v in v dd(max.) pins not under test = 0v -1 1 -1 1 ua intput leakage current (i/o pins) l lo v out 0, v out v dd(max.) dq# in h - z., dout disabled -1.5 1.5 -1.5 1.5 ua output low voltage v ol i ol = 2ma 0.4 0.4 v 4 output high voltage v oh i oh = -2ma 2.4 2.4 v 4 3 3 3 3 3 3 3 3 3 3 notes : 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2. i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) . 4. for lvttl compatible.
document : 1g5-0154 rev.1 page 6 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram ac characteristics : (ta = 0 to 70c v dd = 3.3v 0.3v ,v ss = 0v) test conditions for lvttl compatible : ac input levels (v ih /v il ) 2.0/0.8v input timing reference level/ output timing reference level 1.4v input rise and fall time 1ns output load condition 50pf w ac test load circuits (for lvttl interface) : v ddq v ddq v out device under test 50pf z = 50
document : 1g5-0154 rev.1 page 7 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram ac characteristics : (ta = 0 to 70c v dd = 3.3v0.3v, v ss = 0v) symbol a.c. parameter -75 -8h unit note min. max. min. max. t rc row cycle time 60 70 ns t rcd ras to cas delay 20 20 t rp precharge to refresh/row activate command 15 20 t rrd row activate to row activate delay 15 20 t ras row activate to precharge time 37.5 100,000 50 100,000 t ck2 clock cycle time cl2 7.5 10 ns t ck3 cl3 7.5 10 t ch clock high time 2.25 3 t cl clock low time 2.25 3 t ac2 access time from clk (positive edge) cl2 5 6 t ac3 cl3 5 6 t t transition time of clk (rise and fall) 1 10 1 10 t ccd cas to cas delay time 1 1 clk t oh data output hold time 2.5 3 ns t lz data output low impedance 0 0 t hz2 data output high impedance cl2 4 6 9 t hz3 cl3 4 6 t is data/address/control input setup time 1 2 t ih data/address/control input hold time 0.5 1 t srx minimum cke ?high?for self-refresh exit 1 1 clk t pde power down exit set-up time 2 2 ns t rsc mode register set cycle 2 2 clk t dpl data-in to precharge 2 1 clk t dal2 data-in to act (ref) command cl2 2clk+t rp 1clk+t rp ns t dal3 cl3 2clk+t rp 1clk+t rp t bdl last data in to burst stop 1 1 clk t ref refresh time 64 64 ms
document : 1g5-0154 rev.1 page 8 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram basic features and function description 1.simplified state diagram self refresh mrs mode register set idle auto refresh ref a c t cke cke b s t power down active power down row active read cke cke read read suspend cke cke reada reada suspend read with auto precharge cke cke write (write recovery) write write suspend writea write a suspend cke cke write with auto precharge power on precharge precharge p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) r e a d w i t h w r i t e w i t h a u t o p r e c h a r g e a u t o p r e c h a r g e r e a d b s t w r i t e r e a d w i t h a u t o p r e c h a r g e ( w r i t e r e c o v e r y ) r e a d w i t h a u t o p r e c h a r g e write read (write recovery) p r e c k e c k e automatic sequence manual input note: after the auto refresh operation, precharge operation is performed automatically and enter the idle state. s e l f e n t r y s e l f e x i t w r i t e r e c o v e r y
document : 1g5-0154 rev.1 page 9 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 2. truth table 2.1 command truth table 2.2 dqm truth table 2.3 cke truth table h : high level, l : low level x : high or low level (don?t care), v : valid data input function symbol cke cs ras cas we ba (1) a10 a11 a9 - a0 n -1 n device deselect desl h x h x x x x x x no operation nop h x l h h h x x x mode register set mrs h x l l l l l l v bank activate act h x l l h h v v v read read h x l h l h v l v read with auto precharge reada h x l h l h v h v write writ h x l h l l v l v write with auto precharge writa h x l h l l v h v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x burst stop bst h x l h h l x x x cbr (auto) refresh ref h h l l l h x x x self refresh self h l l l l h x x x function symbol cke dqm n -1 n -1 u l data write/output enable enb h x l data mask/output disable mask h x h upper byte write enable/output enable enbu h x l x lower byte write enable/output enable enbl h x x l upper byte write inhibit/output disable masku h x h x lower byte write inhibit/output disable maskl h x x h current state function symbol cke cs ras cas we add - ress n - 1 n activating clock suspend mode entry h l x x x x x any clock suspend l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x self refresh self refresh exit l h l h h h x l h h x x x x idle power down entry h l x x x x x power down power down exit l h x x x x x
document : 1g5-0154 rev.1 page 10 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 2.4 operative command table notes 1 current state cs ras cas we address command action notes idle h x x x x desl nop or power down 2 l h h x x nop or bst nop or power down 2 l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h br, ra act row active l l h l ba, a10 pre/pall nop l l l h x ref/self refresh or self refresh 4 l l l l op - code mps mode register access row active h x x x x desl nop l h h x x nop or bst nop l h l h ba, ca, a10 read/reada begin read : determine ap 5 l h l l ba, ca, a10 writ/writa begin write : determine ap 5 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall precharge 6 l l l h x ref/self illegal l l l l op - code mrs illegal read h x x x x desl continue burst to end row active l h h h x nop continue burst to end row active l h h l x bst burst end row active l h l h ba, ca, a10 read/reada term burst, new read : determine ap 7 l h l l ba, ca, a10 writ/writa term burst, start write : determine ap 7,8 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall term burst, precharging l l l h x ref/self illegal l l l l op - code mrs illegal write h x x x x desl continue burst to end write recovering l h h h x nop continue burst to end write recovering l h h l x bst burst stop row active l h l h ba, ca, a10 read/reada term burst, start read : determine ap 7,8 l h l l ba, ca, a10 writ/writa term burst, new write : determine ap 7 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall term burst, precharging 9 l l l h x ref/self illegal l l l l op - code mrs illegal ? ? ? ? ? ? (1/3)
document : 1g5-0154 rev.1 page 11 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram current state cs ras ca we address command action notes read with auto precharge h x x x x desl continue burst to end prcharging l h h h x nop continue burst to end prcharging l h h l x bst illegal for single bank, but legal for multibanks interleave l h l h ba, ca, a10 read/reada illegal for single bank, but legal for multibanks interleave l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 l l l h x pef/self illegal l l l l op - code mrs illegal write with auto precharge h x x x x desl continue burst to endwrite recovering with auto precharge l h h h x nop continue burst to endwrite recovering with auto precharge l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal for single bank, but legal for multibanks interleave l h l l ba, ca, a10 writ/writa illegal for single bank, but legal for multibanks interleave l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 l l l h x pef/self illegal l l l l op - code mrs illegal precharging h x x x x desl nopenter idle after t rp l h h h x nop nopenter idle after t rp l h h l x bst nopenter idle after t rp l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall nopenter idle after t rp l l l h x pef/self illegal l l l l op - code mrs illegal row activating h x x x x desl nopenter row active idle after t rcd l h h h x nop nopenter row active idle after t rcd l h h l x bst nopenter row active idle after t rcd l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3,9 l l h l ba, a10 pre/pall illegal 3 l l l h x pef/self illegal l l l l op - code mrs illegal ? ? ? ? ? ? ? ? ? ? ? (2/3)
document : 1g5-0154 rev.1 page 12 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram (3/3) note 1. all entries assume that cke was active (high level) during the preceding clock cycle. 2. if both banks are idle, and cke is inactive (low level), the device will enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if both banks are idle, and cke is inactive (low level), the device will enter self refresh mode. all input buffers except cke will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which don?t satisfy t dpl . 10. illegal if t rrd is not satisfied. 11. illegal for single bank, but for multibanks interleave current state cs ras ca we address command action notes write recovering h x x x x desl nop enter row active after t dpl l h h h x nop nop enter row active after t dpl l h h l x bst nop enter row active after t dpl l h l h ba, ca, a10 read/reada start read, determine ap 8 l h l l ba, ca, a10 writ/writa new write, determine ap l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 l l l h x pef/self illegal l l l l op - code mrs illegal write recovering with auto precharge h x x x x desl nop enter precharge after t dpl l h h h x nop nop enter precharge after t dpl l h h l x bst nop enter precharge after t dpl l h l h ba, ca, a10 read/reada illegal 3,8 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 ref/pall illegal 3 l l l h x ref/self illegal l l l l op - code mrs illegal auto refreshing h x x x x desl nop enter idle after t rc l h h x x nop/bst nop enter idle after t rc l h l x x read/writ illegal l l h x x act/pre/pall illegal l l l x x ref/self/mrs illegal mode regis- ter setting h x x x x desl nop enter idle after 2 clocks l h h h x nop nop enter idle after 2 clocks l h h l x bst illegal l h l x x read/write illegal l l x x x act/pre/ pall/ illegal ? ? ? ? ? ? ? ?
document : 1g5-0154 rev.1 page 13 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 2.5 command truth table for cke note 1 note 1. h : hight level, l : low level, x : high or low level (don't care) 2. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 3. power down and self refresh can be entered only from the both banks idle state. 4. must be legal command as defined in operative command table. 5. iiiegal if t srex is not satisfied. current state cke n - 1 ras n cs ras cas we address action notes self refresh (s.r.) h x x x x x x invalid, clk (n-1)would exit s.r. l h h x x x x s.r. recovery 2 l h l h h x x s.r. recovery 2 l h l h l x x illegal l h l l x x x illegal l l x x x x x maintain s.r. self refresh recovery h h h x x x x idle after t rc h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x begin clock suspend next cycle 5 h l l h h x x begin clock suspend next cycle 5 h l l h l x x illegal h l l l x x x illegal l h x x x x x exit clock suspend next cycle 2 l l x x x x x maintain clock suspend power down (p.d.) h x x x x x invalid, clk(n-1) would exit p.d. l h x x x x x exit p.d. idle 2 l l x x x x x maintain power down mode both banks idle h h h x x x refer to operations in operative command table h h l h x x refer to operations in operative command table h h l l h x refer to operations in operative command table h h l l l h x auto refresh h h l l l l op-code refer to operations in operative command table h l h x x x refer to operations in operative command table h l l h x x refer to operations in operative command table h l l l h x refer to operations in operative command table h l l l l h x self refresh 3 h l l l l l op-code refer to operations in operative command table l x x x x x x power down 3 any state other than listed above h h x x x x x refer to operations in operative command table h l x x x x x begin clock suspend next cycle 4 l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend ?
document : 1g5-0154 rev.1 page 14 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 5.m ode register (address input for mode set) 0 0 0 0 1 13 12 11 10 9 8 5 4 3 2 1 0 jedec standard test set x x 1 0 0 11 10 9 8 7 6 5 4 3 2 1 0 burst read and single write (for write through cache) ltmode wt bl x x 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 burst read and burst write x = don?t care ltmode wt bl burst length bits2 - 0 wt = 1 wt = 0 000 001 010 011 100 101 110 111 1 2 4 8 r r r full page 1 2 4 8 r r r r wrap type 0 1 sequential interleave latency bits6 - 4 cas iatency 000 001 010 011 100 101 110 111 r r 2 3 r r r r mode remark r : reserved 7 6 0 0 reserved 13 x x 13 12 x x 12
document : 1g5-0154 rev.1 page 15 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 5.1 burst length and sequence (burst of two) (burst of four) (burst of eight) full page burst is an extension of the above tables of sequential addressing, with the length being 2048 / 1024 / 512 for 32m x 4 / 16m x 8 / 8m x16 devices, respectively. starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 starting address (column address a1 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 starting address (column address a2 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
document : 1g5-0154 rev.1 page 16 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram a12 a13 result 0 0 select bank a ?activate ? command 0 1 select bank b ?activate? command 1 0 select bank c ?activate? command 1 1 select bank d ?activate? command 0 disables auto - precharge (end of burst) 1 enables auto - precharge (end of burst) (activate command) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 6 address bits of bank-select and precharge 6.1 quad banks controlled by a12 & a13 a10 a12 a13 result 0 0 0 precharge bank a 0 0 1 precharge bank b 0 1 0 precharge bank c 0 1 1 precharge bank d 1 x x precharge all banks a12 a13 result 0 0 enables read/write commands for bank a 0 1 enables read/write commands for bank b 1 0 enables read/write commands for bank c 1 1 enables read/write commands for bank d row (precharge command) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ( cas strobes) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 col. row
document : 1g5-0154 rev.1 page 17 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 7.precharge the precharge command can be asserted anytime after t ras(min) is satisfied. soon after the precharge command is asserted, the precharge operation is performed and the synchronous dram enters the idle state after t rp(min.) is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows. prechargee in order to write all data to the memory cell correctly, the asynchronous parameter ?t dpl ? must be satis- fied. the t dpl( min. ) specification defines the earliest time that a precharge command can be asserted. the minimum number of clocks can be calculated by dividing t dpl(min.) by the clock cycle time. in summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. cas latency read write 2 -1 + t dpl(min.) 3 -2 + t dpl(min.) burst lengh=4 clk command cas latency = 2 dq command cas latency = 3 dq cas latency = 2 : one clock earlier than the last output data. 3 : two clocks earlier than the last output data. (t ras is satisfied) hi - z q0 q3 q2 q1 pre q0 q3 q2 q1 read read t0 t1 t2 t3 t4 t5 t6 t7 pre hi - z
document : 1g5-0154 rev.1 page 18 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 8.auto precharge d uring a read or write command cycle, a10 controls whether auto precharge is selected. if a10 is high in the read or write command (read with auto precharge command or write with auto precharge com- mand), auto precharge is selected and begins automatically after the burst access. in the write cycle, t dal(min.) must be satisfied before asserting the next activate command to the bank being precharged. when using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. once auto precharge has started, an activate command to the bank can be asserted after t rp has been satisfied. a read or write command without auto - precharge can be terminated in the midst of a burst operation. however, a read or write command with auto - precharge can not be interrupted by the same bank com- mands before the entire burst operation is completed. therefore use of the same bank read, write, pre- charge or burst stop command is prohibited during a read or write cycle with auto - precharge. it should be noted that the device will not respond to the auto - precharge command if the device is programmed for full page burst read or write cycles. the timing when the auto precharge cycle begins depends both on both the cas iatency programmed into the mode register and whether the cycle is read or write. 8.1 read with auto precharge during a reada cycle, the auto precharge begins one clock earlier (cl = 2) or two clocks earlier (cl = 3) than the last word output. read with auto precharge burst lengh = 4 clk command cas latency = 2 dq command cas latency = 3 dq remark reada means read with auto precharge hi - z auto precharge starts qb0 qb3 qb2 qb1 reada b reada b t0 t1 t2 t3 t4 t5 t6 t7 auto precharge starts hi - z t8 qb0 qb3 qb2 qb1 no new command to bank b no new command to bank b
document : 1g5-0154 rev.1 page 19 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 8.2 write with auto precharge during a write cycle, the auto precharge starts at the timing that is equal to the value of t dpl(min.) after the last data word input to the device. write with auto prechrge in summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means clocks after the reference. cas latency read write 2 -1 + t dpl(min.) 3 -2 + t dpl(min.) burst lengh = 4 clk command cas latency = 2 dq command cas latency = 3 dq remark writa means write with auto precharge hi - z db0 db3 db2 db1 writa b writa b t0 t1 t 2 t3 t4 t5 t6 t7 hi - z_ t8 t dpl t dpl db0 db3 db2 db1 auto precharge starts auto precharge starts no new command to bank b no new command to bank b
document : 1g5-0154 rev.1 page 20 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 8.3 multibank operation- read with auto precharge during a reada cycle interrupted by a read, write command of another banks, the auto-pre- charge scheduled time would not be changed. clk command cas latency=2 dq command cas latency=3 dq hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 reada a read b burst lengh=8 auto precharge bank a starts qa0 qa1 qb0 qb2 qb3 qb4 qb5 qb6 qb7 qb1 read b auto precharge bank a starts hi-z qa0 qa1 qb0 qb2 qb3 qb4 qb5 qb6 qb7 qb1 reada a multibank operation similiar top.21
document : 1g5-0154 rev.1 page 21 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 8.4 multibank operation- write with auto precharge during a writea cycle interrupted by a read, write command of another banks, the auto-pre- charge scheduled time would not be changed. clk command cas latency=2 dq command cas latency=3 dq hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 burst lengh=8 auto precharge bank a starts writa a read b da0 da1 db0 db1 db2 db3 db4 db5 hi-z auto precharge bank a starts writa a read b da0 da1 db0 db1 db2 db3 db4 clk command cas latency=2 dq command cas latency=3 dq hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 burst lengh=8 auto precharge bank a starts writa a write b da0 da1 db0 db1 db2 db3 db4 db6 db7 hi-z auto precharge bank a starts writa a write b da0 da1 db0 db1 db2 db3 db4 db5 db6 db7 db5 multibank operation multibank operation
document : 1g5-0154 rev.1 page 22 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 9.read/write command interval 9.1 read to read command interval during a read cycle when a new read command is asserted, it will be effective after the cas latency, even if the previous read operation has not completed. read will be interrupted by another read. each read command can be asserted in every clock without any restriction. burst lengh=4, cas latency=2 clk command dq qa0 qb2 qb1 qb0 read a t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t8 1 cycle qb3 read b burst lengh=4, cas latency=2 clk command dq qa0 qb2 qb1 qb0 write a t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t8 1 cycle qb3 write b write to write command interval 9.2 write to write command interval during a write cycle, when a new write command is asserted, the previous burst will terminated and the new burst will begin with a new write command. write will be interrupted by another write. each write command can be asserted in every clock without any restriction. read to read command interval
document : 1g5-0154 rev.1 page 23 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 9.3 write to read command interval the write command to read command interval is also a minimum of 1 cycle. only the write data before the read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . write to read command interval 9.4 read to write command interval during a read cycle, read can be interrupted by write. dqm must be in high at least 3 clocks prior to the write command. there is a restriction to avoid a data conflict. the data bus must be hi-z using dqm before write. burst lengh=4 clk command cas latency=2 dq command cas latency=3 dq qb0 qb3 qb2 qb1 write a write a t0 t1 t2 t3 t4 t5 t6 t7 t8 qb0 qb3 qb2 qb1 1 cycle read b da0 read b da0 hi-z hi-z
document : 1g5-0154 rev.1 page 24 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram read to write command interval cas latency=2 clk command dqm dq hi-z d0 d3 d2 d1 read t0 t1 t2 t3 t4 t5 t6 t7 t8 1 cycle write burst length=8, cas latency=2 clk command dqm dq q0 read t0 t1 t2 t3 t4 t5 t6 t7 t8 write t9 necessary q2 q1 d0 d2 d1 hi-z is example: burst length=4, cas latency=3 clk command dqm dq read t0 t1 t2 t3 t4 t5 t6 t7 t8 write necessary d0 d2 d1 hi-z is q2 the minimum command interval = (4+1) cycles
document : 1g5-0154 rev.1 page 25 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 10.burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. 10.1 burst stop command during a read burst. when the burst stop command is asserted, the burst read data are termi- nated and the data bus goes to high-impedance after the cas latency from the burst stop com- mand. during a write burst, when the burst stop command is asserted, any data provided at that cycle will not be written. the burst write is effectively terminated and no further data can be written until a new write command is asserted. burst termination remark bst: burst stop command remark bst: burst command burst lengh=x, cas intency=2,3 clk command cas latency=2 dq cas latency=3 dq q0 q2 q1 read t0 t1 t2 t3 t4 t5 t6 t7 bst hi-z q0 q2 q1 hi-z burst lengh=x, cas latency=2,3 clk command cas latency=2,3 dq q0 q2 q1 write t0 t1 t2 t3 t4 t5 t6 t7 bst hi-z_ q0
document : 1g5-0154 rev.1 page 26 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 10.2 precharge termination 10.2.1 precharge termination in read cycle during read cycle, the burst read operation is terminated by a precharge command. when the precharge command is asserted, the burst read operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. when cas latency is 2,the read data will remain valid until one clock after the precharge com- mand. when cas latency is 3, the read data will remain valid until two clocks after the precharge com- mand. precharge termination in read cycle burst lengh= x clk command cas latency=2 dq hi-z read t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp pre act dq read pre act t rp cas latency=3 q0 q3 q2 q1 hi-z q0 q3 q2 q1 command
document : 1g5-0154 rev.1 page 27 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram 10.2.2 precharge termination in write cycle during write cycle, the burst write operation is terminated by a precharge com- mand. when the precharge command is asserted, the burst write operation is termi- nated and precharge starts. the same bank can be activated again after t rp from the precharge command. the dqm must be high to mask invalid data in. during write cycle, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the pre- charge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. precharge termination in write cycle burst lengh = x clk command cas latency = 2 dqm hi - z write t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp pre act dq write pre act t rp cas latency = 3 hi - z d0 d3 d2 d1 d0 d3 d2 d1 dqm d4 d4 command dq
document : 1g5-0154 rev.1 page 28 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram , timing diagram
document : 1g5-0154 rev.1 page 29 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 0 mode register set clk cke cs ras cas we bs a10 add dqm dq command mode register set command all banks precharge command t rp t rsc hi-z address key
document : 1g5-0154 rev.1 page 30 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t ch t cl t cks t cms t cmh t as t ah begin auto precharge bank a begin auto precharge bank b t ckh t ck2 ac parameters for write timing (1 of 2) clk cke cs ras cas we bs a10 add dqm dq t rcd t rrd t rc t dal qaa0 qaa1 qaa2 qaa3 qba0 qba1 qba2 qba3 qab0 qab1 qab2 qab3 activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write without auto precharge command bank a t ds t dh t dpl rp t precharge command bank a activate command bank a burst length=4, cas latency=2 (bank d) activate command bank b (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 31 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t ch t cl t cks t cms t cmh t as t ah begin auto precharge bank a begin auto precharge bank b t ckh t ck3 ac parameters for write timing (2 of 2) clk cke cs ras cas we bs a10 add dqm dq t rcd t rrd t rc t dal qaa0 qaa1 qaa2 qaa3 qba0 qba1 qba2 qba3 qab0 qab1 qab2 qab3 activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write without auto precharge command bank a t ds t dh t dpl rp t precharge command bank a activate command bank a burst length=4, cas latency=3,4 (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 32 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ac parameters for read timing (1 of 2) clk cke cs ras cas we bs a10 add dqm dq burst length=2, cas latency=2 t ch t cl t ck2 begin auto precharge bank b t ckh t cks t cms t cmh t ah t as t rrd t ras t rc t rcd t ac2 t lz t oh t ac2 t oh t hz t rp t hz hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a qaa0 qaa1 qba0 qba1 (bank d) (bank d) (bank d) command
document : 1g5-0154 rev.1 page 33 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ac parameters for read timing (2 of 2) clk cke cs ras cas we bs a10 add dqm dq burst length=2, cas latency=3 t lz t hz hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a t ch t cl t cks t ck3 t cms t cmh t ah t as t rrd t ras t rc t rp t rcd t ac3 t oh t ac3 qaa0 qaa1 qba0 qba1 t oh t hz command t ckh begin auto precharge bank b (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 34 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 power on sequence and auto refresh (cbr) clk cke cs ras c as we bs a10 add dqm dq high level is required minimum of 2 refresh cycles are required t rsc t rp high level is necessary t rc address key inputs be stable for 100us precharge all banks must command 1st auto command refresh 2nd auto refresh command mode set command command register hi-z
document : 1g5-0154 rev.1 page 35 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst read (using cke) (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t hz activate bank a command read bank a command clock 2 cycles hi-z qaa0 qaa1 qaa2 qaa3 raa caa raa t ck2 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=2
document : 1g5-0154 rev.1 page 36 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst read (using cke) (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t hz activate bank a command read bank a command clock 2 cycles hi-z qaa0 qaa1 qaa2 qaa3 raa raa t ck3 clock suspended 1 cycles suspended clock 3 cycles suspended burst length=4, cas latency=3 caa
document : 1g5-0154 rev.1 page 37 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst write (using cke) (1 of 2) clk cke cs ras c as we bs a10 add dqm dq activate bank a command write bank a command clock 2 cycles hi-z raa caa raa t ck2 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=2 daa0 daa1 daa2 daa3
document : 1g5-0154 rev.1 page 38 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst write (using cke) (2 of 2) clk cke cs ras c as we bs a10 add dqm dq raa raa t ck burst length=4, cas latency=3 caa activate bank a command write bank a command clock 2 cycles hi-z clock suspended 1 cycle suspended clock 3 cycles suspended daa0 daa1 daa2 daa3
document : 1g5-0154 rev.1 page 39 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 power down mode and clock mask clk cke cs ras c as we bs a10 add dqm dq raa raa t ck2 burst length=4, cas latency=2 activate bank a command power down mode entry power down bank a hi-z active standby read clock mask caa t cks t ckh valid t cks raa qaa0 qaa1 qaa2 qaa3 mode exit command start clock mask end t hz precharge command power down mode entry precharge standby power mode down exit command clk can be stopped *
document : 1g5-0154 rev.1 page 40 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto refresh (cbr) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 precharge all banks command cbr refresh hi-z cbr refresh command activate command read raa caa raa q0 q1 q2 q3 command command t rp t rc t rc
document : 1g5-0154 rev.1 page 41 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 self refresh (entry and exit) clk cke cs ras c as we bs a10 add dqm dq t srx all banks self refresh hi-z self refresh exit self refresh entry exit t rc t cks t srx t cks t rc must be idle self refresh entry activate command clk can be stopped * * clock can be stopped at cke=low. if clock is stopped, it must be restarted/stable for 4 clock cycles before cke=high
document : 1g5-0154 rev.1 page 42 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column read (page within same bank)(1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 precharge bank a command read hi-z activate read raa qad0 command command raa caa raa cab cac rad rad cad qaa0 qaa1 qaa2 qaa3 qab0 qab1 qac0 qac1 qac2 qac3 qad1 qad2 qad3 bank a read command bank a read command bank a precharge command bank a bank a command bank a
document : 1g5-0154 rev.1 page 43 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column read (page within same bank)(2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck3 burst length=4, cas latency=3 activate bank a command read hi-z activate read command command raa caa cab cac rad cad qac2 qac3 qaa0 qaa1 qaa2 qaa3 qab0 qab1 qac0 qac1 bank a read command bank a precharge command bank a bank a command bank a rad read command bank a raa
document : 1g5-0154 rev.1 page 44 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column write (page within same bank) (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank b command write hi-z activate write command command ra ca ra cb cc rd cd dc2 dc3 da1 da2 da3 db0 db1 dc0 dc1 bank b write command bank b precharge command bank b bank b command bank b write command bank b rd dd2 dd3 dd0 dd1 da0 (bank d) (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 45 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column write (page within same bank) (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck burst length=4, cas latency=3 activate bank b command write hi-z activate command ra ca ra cb cc cd rd bank b write command bank b precharge command bank b command bank b write command bank b rd write command bank b dc2 dc3 da1 da2 da3 db0 db1 dc0 dc1 da0 dd0 dd1 (bank d) (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 46 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row read (interleaving banks)(1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=8, cas latency=2 activate bank b command read hi-z command qaa0 qaa1 qba1 qba2 qba3 qba4 qba5 qba6 qba7 bank b activate command bank a active command bank b read command bank a qbb1 qbb0 qba0 read command bank b qaa3 qaa4 qaa5 qaa6 qaa7 qaa2 precharge command bank b t rcd t ac2 t rp high (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 47 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row read (interleaving banks) (2 of 3) clk cke cs ras c as we bs a10 add dqm dq t ck3 burs tlength=8, cas latency=3 activate bank b command read hi-z command qaa0 qaa1 qba1 qba2 qba3 qba4 qba5 qba6 qba7 bank b activate command bank a precharge command bank b qbb0 qba0 read command bank b qaa3 qaa4 qaa5 qaa6 qaa7 qaa2 read command bank a t rcd t ac3 t rp high activate bank b command precharge command bank a (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 48 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row write (interleaving banks) (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=8, cas latency=2 activate bank a command write hi-z command qba0 qba1 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 bank a activate command bank b active command bank a write command bank b qab3 qab2 qaa0 write command bank a qba3 qba4 qba5 qba6 qba7 qba2 precharge command bank a t rcd t rp high t dpl t dpl qab0 qab1 qab4 precharge command bank b (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 49 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row write (interleaving banks) (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck burst length=8, cas latency=3 activate bank a command write hi-z command qaa7 qba0 qaa0 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 bank a activate command bank b qab2 qab1 activate command bank a qba2 qba3 qba4 qba5 qba6 qba1 write command bank b rba t rcd t rp high t dpl t dpl qbb7 qab0 qab3 write command bank a precharge command bank a precharge command bank b (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 50 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read and write cycle (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command write hi-z command dab3 qac0 qaa0 qaa1 qaa2 qaa3 dab0 dab1 bank a write command bank a read command bank a qac3 qac1 the read data the write data is masked with a zero clock raa raa cab cac caa latency is masked with two clocks latency
document : 1g5-0154 rev.1 page 51 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read and write cycle (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck3 burst length=4, cas latency=3 activate bank a command read hi-z command dab3 qac0 qaa0 qaa1 qaa2 qaa3 dab0 dab1 bank a write command bank a qac3 qac1 the read data the write data is masked with a zero clock raa latency is masked with a two clock latency raa cab caa cac read command bank a
document : 1g5-0154 rev.1 page 52 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column read cycle (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command read hi-z command qbb1 qbd0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 bank a read command bank b qbd2 qbd1 precharge ra ra ra cb ra ca cb cc cb cd qab1 qbc0 qbc1 qbd3 activate command bank b read command bank b qbb0 qab0 read command bank b read command bank a read command bank b precharge command bank a command bank b t rcd t ac2 (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 53 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column read cycle (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qbb1 qab2 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qab3 precharge ra ra ra ca ra ca cb cc cb qab1 qbc0 qbc1 read command bank a read command bank b qbb0 qab0 read command bank b read command bank b read command bank a precharge command bank b command bank a t rrd activate command bank b t rcd t ac3 (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 54 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column write cycle (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z dbb1 dbd0 daa0 daa1 daa2 daa3 dba0 dba1 dbd1 precharge ra ra ra ca ra ca cb cc cb dab1 dbc0 dbc1 write command bank a write command bank b dbb0 dab0 command write command bank b write command bank a precharge command bank a command bank b t rrd activate command bank b t rcd t rp cb dbd2 dbd3 write bank b t dpl write command bank b (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 55 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column write cycle (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck burst length=4, cas latency=3 activate bank a command hi-z qbb1 qbd0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbd1 precharge ra ra ra ca ra ca cb cc cb qab1 qbc0 qbc1 write command bank a write command bank b qbb0 qab0 write command bank b write command bank b write command bank a write command bank b command bank a t rrd activate command bank b t rcd cd t dpl t rp qbd2 qbd3 t dpl precharge command bank b (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 56 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after read burst (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z qba3 qbb0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbb1 read with ra ra ca ra ca cb rb cb qab3 qab0 qab1 activate command bank b qba2 qab2 read with command bank a activate command bank b read with command bank b activate command bank a command bank a read with auto precharge bank b rc qbb2 qbb3 rb rc ra cc qac0 qac2 read bank a command command qac1 auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 57 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after write burst (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qba3 qaa0 qaa1 qaa2 qaa3 qba0 qba1 ra ra ra qab3 qab0 qab1 read command bank a read with command bank b qba2 qab2 command bank a activate command bank b qbb0 ra ca ca rbb cb auto precharge start auto precharge bank b start auto bank a start auto precharge bank b high rb cb qbb1 qbb2 activate command bank b write with auto precharge auto precharge command bank b (bank d) (bank d) (bank d) (bank d) read with rb precharge (bank d) (bank d)
document : 1g5-0154 rev.1 page 58 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after write burst (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z qba3 qbb0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbb1 ra ra ra qab3 qab0 qab1 write command bank a write with command bank b qba2 qab2 write with command bank a activate command bank b write with command bank b activate command bank b qbb2 qbb3 rb ra ca cb ca rb cb auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high rc rc cc qac0 qac1 qac2 qac3 activate command bank a write with auto precharge bank a start auto precharge bank a (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 59 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after write burst (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck burst length=4, cas latency=3 activate bank a command hi-z qba3 qaa0 qaa1 qaa2 qaa3 qba0 qba1 ra ra ra qab3 qab0 qab1 read command bank a read with command bank b qba2 qab2 command bank a activate command bank b qbb0 ra ca ca rbb cb auto precharge start auto precharge bank b start auto bank a start auto precharge bank b high rb cb qbb1 qbb2 activate command bank b write with auto precharge auto precharge command bank b (bank d) (bank d) (bank d) (bank d) read with rb precharge qbb3 (bank d) (bank d)
document : 1g5-0154 rev.1 page 60 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page read cycle (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command read hi-z command ra qaa+1 bank a the burst counter wraps burst stop read command bank b qaa full page burst operation does not ra ca rb t rp high activate command bank b ra rb ca qaa+2 qaa-2 qaa-1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+4 qba+51 qba+6 activate command bank b from the highest order page address back to zero during this time interval terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address command precharge command bank b ra (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 61 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page read cycle (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck3 burst length=full page, cas latency=3 activate bank a command read hi-z command ra qaa+1 bank a the burst counter wraps burst stop read command bank b qaa full page burst operation ra ca rb high activate command bank b ra rb ca qaa+2 qaa-2 qaa-1 qaa qaa+1 qba0 qba+1 qba+2 qba+3 qba+4 qba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address ra (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 62 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page write cycle (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command write hi-z command ra qaa+1 bank a the burst counter wraps burst stop write command bank b qaa full page burst operation ra ca rb t bdl high activate command bank b ra rb ca qaa+2 qaa+3 qaa-1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+4 qba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address qba+6 data is ignored ra (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 63 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page write cycle (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck burst length=full page, cas latency=3 activate bank a command write hi-z command ra daa+1 bank a the burst counter wraps burst stop write command bank b daa full page burst operation ra t bdl high activate command bank b daa+2 daa+3 daa-1 daa daa+1 dba dba+1 dba+2 dba+3 dba+4 dba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address ra rb ca ra ca rb data is ignored. (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 64 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 byte write operation clk cke cs ras c as we bs a10 add ldqm udqm t ck2 burst length = 4, cas latency = 2 hi-z raa raa high activate caa cab caz dq0~dq7 command bank a read command bank a upper byte is masked lower byte is masked write command bank a write upper is masked read command bank a lower byte is masked lower byte is masked dq8~dq15
document : 1g5-0154 rev.1 page 65 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 burst read and single write operation clk cke cs ras c as we bs a10 add ldqm udqm t ck2 burst length = 4, cas latency = 2 hi-z raa raa high activate caa cab cad dq0~dq7 command bank a read command bank a single write single write read command bank a lower byte is masked upper byte is masked dq8~dq15 cac cae command bank a command bank a lower byte is masked single write command bank a
document : 1g5-0154 rev.1 page 66 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page random column read clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command activate hi-z command ra qba0 bank b read command bank b qaa0 ra activate command bank b qab0 qab1 qbb0 qbb1 qac0 qac1 qac2 qbc0 qbc1 qbc2 read command bank a precharge cc cc rb ra ra ca ca cb cb rb t rp read command bank b read command bank a read command bank a read command bank b command bank b (precharge termination) (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 67 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page random column write clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command activate hi-z command ra qba0 bank b write command bank b qaa0 ra activate command bank b qab0 qab1 qbb0 qbb1 qac0 qac1 qac2 qbc0 qbc1 qbc2 write command bank a precharge cc cc rb ra ra ca ca cb cb rb t rp write command bank b write command bank a write command bank a write command bank b command bank b (precharge termination) write data is masked (bank d) (bank d) (bank d) (bank d) (bank d) (bank d)
document : 1g5-0154 rev.1 page 68 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 precharge termination of a burst (1 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck2 burst length=4,8 or full page, cas latency=2 activate bank a command write hi-z command raa bank a activate command bank a read command bank a rac cab rab rab rac precharge termination of a write burst. write data is masked. precharge command read command bank a precharge command bank a precharge termination high raa cac caa qaa1 qaa0 qaa2 da3 qab0 qab1 qab2 qac0 qac1 qac2 t dpl t rp t rp t rp bank a of a read burst. activate command bank a precharge command bank a
document : 1g5-0154 rev.1 page 69 vis VG36128401A preliminary vg36128801a vg36128161a cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 precharge termination of a burst (2 of 2) clk cke cs ras c as we bs a10 add dqm dq t ck3 burst length=4,8 or full page, cas latency=3 activate bank a command write hi-z command raa bank a activate command bank a cab rab rab rac precharge command read command bank a high raa rac caa daa1 daa0 qab0 qab1 qab2 qab3 t dpl t rp bank a activate command bank a activate command bank a t rcd t rp write data is masked precharge termination of a write burst. precharge termination of a read burst. t ras

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